1. Field of the Invention
The present invention relates to a semiconductor device, particularly to an Insulated Gate Bipolar Transistor (hereinafter referred to simply as "IGBT") having a configuration in which current flows between both major surfaces of a semiconductor substrate.
2. Description of the Background Art
The IGBT is generally used widely as an element for controlling a motor, for switching of an inverter or the like. The IGBT is a voltage drive element having both properties of low saturation voltage of the bipolar transistor and high-speed switching of the MOSFET, and characterized by small losses in driving power and ON/OFF switching. Since the configuration of the device permits miniaturization of the MOSFET formed on a chip and a decreased ON voltage by an enhanced integration, the use thereof is spreading in these years.
A vertical type n channel IGBT having a planar gate structure is herein presented as one example of conventional IGBTs, and the configuration thereof is described. FIG. 21 shows a cross section of an n channel IGBT having a conventional planar gate structure.
Referring to FIG. 21, an n drift region 1 is formed on the side of a first major surface 14a of a semiconductor substrate 14, and a p base region 2 is selectively formed in n drift region 1. An n emitter region 3 is selectively formed in p base region 2. A region 4 sandwiched between n drift region 1 and n emitter region 3, located in p base region 2, and extending to reach the first major surface 14a is referred to as a channel formation region. A gate dielectric layer 5 is formed on the first major surface 14a to cover channel formation region 4. Gate dielectric layer 5 extends from a portion above n emitter region 3 onto n drift region 1.
P base region 2 and n emitter region 3 are short-circuited by a metal electrode layer (emitter electrode) 8. P base region 2 and metal electrode layer 8 as well as n emitter region 3 and metal electrode layer 8 are in ohmic contact with each other. Further, a p collector region 10 is formed on the side of a second major surface 14b of semiconductor substrate 14. A metal electrode layer (collector electrode) 11 is formed on the second major surface 14b to be in ohmic contact with p collector region 10.
Principles of an operation of the n channel IGBT having the configuration above are described below. Descriptions of following four processes, specifically a process of transition from a cut-off (OFF) state to a conduction (ON) state, a steady state, a process of transition from the ON state to the OFF state, and the OFF state are respectively given below.
(1) Process of Transition from OFF State to ON State
Positive (+) voltage is applied to a gate electrode 6 while voltage which is relatively positive to the voltage at emitter electrode 8 is applied to collector electrode 11. Accordingly, a channel inverted to become n type is formed at channel formation region 4 located in p base region 2. Through this n channel, the electron as one of the carriers is injected from n emitter region 3 into n drift region 1, and the electron flows toward p collector region 10. When the electron reaches p collector region 10, the hole as one of the carriers is injected from p collector region 10 into n drift region 1. The hole flows toward n emitter region 3 to which relatively negative voltage is applied, and the hole reaches a place where the n channel is in contact with n drift region 1. This process is referred to as a storage process, and the time required for this process is referred to as a turn-on delay time (td(on)). The loss of electric power in this process is extremely small and negligible.
Enough carriers are thereafter stored according to the potential difference applied between emitter electrode 8 and collector electrode 11, and a low-resistance state referred to as conductivity modulation due to pairs of electron-hole occurs. Accordingly, the turn-on operation completes. This process is called a rise process, and the time required for this process is called rise time (t(rise)). The loss of electric power in this process is relatively large.
(2) Steady State
The steady state after completion of the turn-on operation is called ON state, and the voltage when current of 100 A/cm.sup.2 flows is called ON voltage. The power loss in this state is called ON loss or steady loss, and expressed by the product of forward voltage drop caused by a resistance component and conduction current. The power loss in ON state is generally exceedingly large. The resistance component in the ON state is determined by the sum of respective resistance components existing at the current path of the device or between emitter electrode 8 and collector electrode 11. The current path of the device is added to the cross sectional view of IGBT in FIG. 21 and shown in FIG. 22 together.
Referring to FIG. 22, references C, E and G in this figure respectively represent terminals of electrodes of the collector, emitter, and gate. Further, Ic, Ih, and Ie respectively represent collector current of IGBT, hole current flowing from n drift region 1 into p base region 2, and electron current flowing from n drift region 1 into n emitter region 3 through channel formation region 4. As shown in FIG. 22, the total resistance component R affecting the ON voltage can be expressed by the following equation. EQU R=Rcn+Rn+Rch+Ra+R.sub.JFET +Rd+R.sub.diode +Rs+Rcp
In the equation above, Rcn is contact resistance between n emitter region 3 and metal electrode layer 8, Rn is resistance of n emitter region 3, Rch is resistance of the channel, Ra is resistance of the storage layer, R.sub.JFET is a resistance component due to JFET (Junction-FIELD EFFECT TRANSISTOR) effect, Rd is resistance of n drift region 1, Rdiode is forward voltage drop of the diode between p collector region 10 and n drift region 1, Rs is resistance of p collector region 10, and Rcp is the contact resistance between p collector region 10 and metal electrode layer 11. There is no JFET in the IGBT having the trench gate structure.
(3) Process of Transition from ON State to OFF State
OFF state is caused by applying voltage of at most the threshold voltage such as negative (-) voltage to gate electrode 6. When the potential at gate electrode 6 is the threshold voltage or less, the n channel formed in ON state disappears. Accordingly, supply of electrons from n emitter region 3 to n drift region 1 is stopped. This process is referred to as a storage process, and the time required for this process is called storage time or turn-off delay time (td(off)). The power loss during this process is extremely small and negligible. Since the supply of electrons is stopped, the density of electrons gradually decreases from a region in the vicinity of n emitter region 3. As a result, the holes injected into n drift region 1 for maintaining an electrically neutral condition also begin to decrease.
Since p base region 2 and n drift region 1 are in a reverse bias state, a depletion layer begins to expand at an interface between p base region 2 and n drift region 1. The depletion layer has a thickness corresponding to a voltage applied between collector electrode 11 and emitter electrode 8. This process is called a fall process. The time required for this process is called fall time and the power loss during this process is called fall loss. The power loss during this period is equivalent to or larger than the turn-on loss and the steady state loss. Holes among carriers outside the depletion region described above pass through the depletion region, pass through a p.sup.+ contact region having high concentration in p base region 2 which is electrically short-circuited with n emitter region 3, and reach metal electrode layer 8. All of the carriers thus disappear and the turn-off completes. This process is called a tail process, the time required for this process is called tail time (t(tail)), and the power loss in this process is called tail loss. The power loss during this process is extremely large.
(4) OFF State
The steady state after completion of the turn-off is referred to as OFF state. Generally, the power loss expressed by the product of the leakage current in this state and the voltage between collector electrode 11 and emitter electrode 8 is extremely small compared with other power losses, and is negligible.
Various power losses are caused in respective processes of conduction/cut-off in the conventional IGBT as described above. In order to achieve a high performance of IGBT, reduction of any one of these losses is desired. In the conventional IGBT, since p base region 2 and n emitter region 3 have the same potential, the pn junction between n drift region 1 and p base region 2 has a low potential. Therefore, storage of carriers decreases to reduce the carrier concentration. As a result, the ON voltage of the IGBT increases, and the power loss in the ON state of the IGBT becomes large.
Further, the IGBT generally has a problem of the latch-up. Description of the latch-up is given referring to FIG. 23. FIG. 23 shows an equivalent circuit to the IGBT. Referring to FIG. 23, an npn bipolar transistor Tr1 is constituted of n emitter region 3, p base region 2, and n drift region 1. A pnp bipolar transistor Tr2 is constituted of p base region 2, n drift region 1 and p collector region 10.
The latch-up is caused, when the parasitic npn bipolar transistor Tr1 is turned on, by the positive feedback between the parasitic npn bipolar transistor Tr1 and the pnp bipolar transistor Tr2. When hole current Ih flows from n drift region 1 to p base region 2, n emitter region 3 and p base region 2 attains a forward bias state due to voltage drop generated by a resistance component R.sub.B in p base region 2. If the voltage drop exceeds the built-in voltage of the npn bipolar transistor (generally about 0.7 V in the case of a bipolar transistor formed on a silicon wafer), electrons are directly injected from n emitter region 3 to p base region 2, resulting in the latch-up. Once the latch-up occurs, the current flowing through the device (IGBT) cannot be controlled by voltage applied to the gate electrode, and the device could be destroyed. Therefore, such latch-up should be avoided.